1. Field of the Invention
This invention relates to a memory cell of a nonvolatile semiconductor memory device, and more particularly to a NAND flash memory with MONOS memory cells.
2. Description of the Related Art
A MONOS memory cell is defined as a memory cell whose charge storage layer is comprised of an insulating material that has a charge trap function.
A MONOS memory cell used in a miniaturized NAND flash memory is comprised of a first insulating film formed on an Si substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control gate electrode formed on the second insulating film.
The first insulating film is referred to as a “tunnel insulating film.” A high electric field is applied to the first insulating film, thereby injecting  charges from the Si substrate into the charge storage layer. A silicon oxynitride film into a part of which nitrogen has been introduced to improve the characteristic is often used as the first insulating film. The reason why the first insulating film is referred to as a tunnel insulating film is that charge movement between the charge storage layer and the Si substrate is made by an FN (Flower-Nordheim) tunneling current flowing through the insulating film at the time of writing/erasing.
Furthermore, a silicon nitride film is used as the charge storage layer because the film functions as an insulating film which captures and emits electrons and holes easily. The silicon nitride film may contain some oxygen.
The second insulating film is referred to as a “block insulating film.” A material whose insulating quality is higher than that of the first insulating film is used for the second insulating film.
Specifically, a high-permittivity (high-k) insulating film comprised of metal oxide or the like is generally used as the second insulating film. The reason why the second insulating film is referred to as a block insulating film is that charge movement between the charge storage layer and the control gate electrode is blocked by the insulating film at the time of writing/erasing. 
Polycrystalline silicon is used for the control gate electrode. In addition to this, a metal, a metal nitride, or a metal carbide gate electrode has been used as the control gate electrode in recent years.
When a MONOS memory cell with a nanometer scale gate length (about 30 nm or less) is formed using these techniques, the following two problems concerning the charge storage layer occur.
The first problem is a charge capture efficiency problem in a silicon nitride film serving as the charge storage layer.
FIG. 1 is an example of plotting the trapped currents obtained from the write/erase characteristics and the theoretical values of the currents flowing through the tunnel insulating film (Fowler-Nordheim tunneling currents) as a function of an effective electric field of the tunnel insulating film in a MONOS (electrode (e.g., metal)-oxide-nitride-oxide-silicon) structure. The symbols indicate data points and the thick solid lines represent a theoretical formula of an electron current and that of a hole current.
As seen from FIG. 1, the silicon nitride film has trapped only an amount of charges much less than the theoretical value of current (Fowler-Nordheim tunneling current) flowing through the tunnel insulating film in the high electric-field region. That is, in the high electric-field region, the charge capture efficiency of  the silicon nitride film decreases.
This tendency is not so serious in trapping holes. When electrons are trapped, the trapped current in a high electric-field region is one digit or more smaller than the injected current (Flower-Nordheim tunneling current), with the result that the charge trapping rate is as low as 10% or less. In this state, without applying a high voltage to the control gate of the memory cell, there is a problem that the desired threshold voltage shift cannot be obtained. Moreover, since the amount of charge passing at the time of writing/erasing is large, this causes the problem of decreasing the reliability of the memory cell.
A second problem is that, as the memory cell is miniaturized further, the number of trapped electrons (in writing) or the number of trapped holes (in erasing) decreases.
Typically, the number of trapped carriers in a memory cell with a gate length of the order of 10 nm is on the order of several tens of carriers. A phenomenon intrinsically occurring with the decrease in the number of carriers in the memory cell causes the following problem: a variation in the retention characteristic increases.
Specifically, for example, as has been discussed in G. Molas, D. Deleruyelle, B. De Salvo, G. Ghibaudo, M. Gely, L. Perniola, D. Lafond, and S. Deleonibus,  “Degradation of Floating-Gate Memory Reliability by Few Electron Phenomena,” IEEE Trans. Electron Devices, 53, 2610 (2006), the retention time of a memory cell varies due to the random nature of the emission of trapped charges. Therefore, when a set of many memory cells is used, a problem of “tail bits” whose retention time is short inevitably occurs.